This paper devoted to report the design and the achievement of an optical communication subsystem with 12 parallel channels in one chip.The system is capable of transmitting 10 Gbps bidirectional date over hundreds of meters.It can provide error detection and correction by using 8B/10B encoding and Cyclical Redundancy Checking (CRC) encoding when only single-channel fails.The design scheme has already passed the simulation in FPGA.This technique is useful to enhance the capability and the reliability of the very short reach (VSR) transmission systems. This paper devoted to report the design and the achievement of an optical communication subsystem with 12 parallel channels in one chip. The system is capable of transmitting 10 Gbps bidirectional date over hundreds of meters. It can provide error detection and correction by using 8B / 10B encoding and Cyclical Redundancy Checking (CRC) encoding when only single-channel fails. The design scheme has already passed the simulation in FPGA. This technique is useful to enhance the capability and the reliability of the very short reach (VSR) transmission systems.