论文部分内容阅读
降低测试期间的功耗是当前学术界和工业界新出现的一个研究领域。在可测试性设计中进行功耗优化的主要原因是数字系统在测试方式的功耗比在系统正常工作方式高很多。测试期间功耗会引发成本增加 ,可靠性降低 ,成品率下降。首先介绍低功耗测试技术中的基本概念和功耗建模方法 ,分析测试过程中功耗升高的原因 ,对已有的几种主要的降低测试功耗方法进行详细分析 ,最后给出一种高性能微处理器的真速低功耗自测试方法
Reducing power consumption during testing is a new area of research currently emerging in academia and industry. The main reason for optimizing power consumption in a testability design is that the power consumption of the digital system in the test mode is much higher than the normal operating mode of the system. Power consumption during the test will lead to increased costs, reduced reliability and reduced yield. Firstly, the basic concepts and modeling methods of power consumption in low-power test technology are introduced. The reasons for the increase of power consumption in the test process are analyzed. Several major methods to reduce test power consumption are analyzed in detail. Finally, High-Performance Microprocessor True-Speed, Low-Power Self-Test Method