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针对FPGA课程实践性强、设计性要求高的特点,通过引入暑期短学期集中培训的方式,尽量压缩理论课堂教学时间,充分给予学生实验室动手实践机会,同时结合项目给定的方式开展实验课堂教学,并通过结果和过程两者相结合的评定方式,充分调动学生学习的积极性。实验过程中通过采用VHDL硬件描述语言实现能够执行相应指令的MCU内核等新实验开发,帮助学生深刻理解微处理器内部结构,特别是让其明白单片机整个系统的核心是一个由系统时钟驱动的全局状态机的逻辑过程。结果表明:该实验的展开使学生更好地掌握FPGA的设计原理、步骤和方法,精通VHDL硬件描述语言的开发和实践和深刻理解汇编指令的执行过程。
In view of the characteristics of FPGA course, such as practicality and high design requirement, this paper tries to reduce the teaching time of theoretical classroom as far as possible by introducing the concentrated training of summer short semester, fully giving students lab practical opportunity and carrying out the experimental class Teaching, and through the combination of the results and the process of assessment, fully mobilize the enthusiasm of students learning. Through the use of VHDL hardware description language during the experiment to achieve the implementation of the corresponding instruction MCU core and other new experimental development to help students understand the internal structure of the microprocessor, in particular, let it understand the core of the microcontroller system is a system-clock driven global State machine logic process. The results show that the experiment expands the students to master the design principles, steps and methods of FPGA, master the development and practice of VHDL hardware description language and profoundly understand the implementation process of assembly instruction.