在分析空频分组码(SFBC)编译码算法的基础上,重点研究了译码算法的工程实现方法。为解决SFBC码译码器现场可编程门阵列(FPGA)实现时的复杂性高、占用资源多的问题,提出了一种基于FPGA的优化译码器结构和实现方案,有效减少了资源占有量,提高了处理速度,并在Xilinx的xc4vlx80芯片上实现了SFBC码译码器,通过时序仿真结果验证了译码结构的有效性和实用性。 On the basis of analyzing coding and decoding algorithm of Space-Frequency Block Code (SFBC), the engineering implementation of decoding algorithm is mainly studied. In order to solve the problem of high complexity and high occupation of resources in the implementation of SFBC code decoder field programmable gate array (FPGA), an FPGA-based optimized decoder structure and implementation scheme is proposed, which effectively reduces the resource consumption , The processing speed is improved, and the SFBC code decoder is implemented on the xc4vlx80 chip of Xilinx. The timing simulation results verify the validity and practicability of the decoding structure.