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逐次逼近(SAR:Successive Approximation Register)ADC广泛应用于低功耗电路系统,为指导低功耗SAR ADC的设计优化,对其D/A转换网络的功耗进行了建模研究。重点针对适用于中高精度应用的R-C组合型D/A转换网络,基于Matlab工具建立了电容阵列的能耗模型,并结合65 nm CMOS工艺,同时考虑电阻梯的静态功耗以及电容阵列的动态功耗,获得了SAR ADC R-C组合型D/A转换网络的功耗模型,在此基础上,以12-bit SAR ADC为设计实例,在考虑无源器件匹配性的前提下,分别针对“5+7”、“6+6”以及“7+5”三种典型的R-C组合结构进行了功耗仿真和比较,研究结果对低功耗SAR ADC的设计和优化具有重要指导意义。
Successive Approximation (SAR) ADCs are widely used in low-power circuit systems. In order to guide the design optimization of low-power SAR ADCs, the power consumption of D / A conversion networks has been modeled. Focusing on the RC combined D / A conversion network suitable for medium and high precision applications, the energy consumption model of the capacitor array is established based on Matlab tools. Combined with the 65 nm CMOS process, the static power consumption of the resistor ladder and the dynamic power of the capacitor array Based on this, a 12-bit SAR ADC is taken as an example to design the power consumption model of SAR ADC RC. In consideration of the matching of passive components, Power simulation and comparison of three typical RC combinational structures, such as +7 “, ” 6 +6 “and ” 7 +5 ". The research results are of great importance to the design and optimization of low power SAR ADC significance.