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A 2-D semi-analytical model of double gate(DG) tunneling field-effect transistor(TFET) is proposed.By aid of introducing two rectangular sources located in the gate dielectric layer and the channel,the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method.The expression of the surface potential is obtained,which is a special function for the infinite series expressions.The influence of the mobile charges on the potential profile is taken into account in the proposed model.On the basis of the potential profile,the shortest tunneling length and the average electrical field can be derived,and the drain current is then constructed by using Kane’s model.In particular,the changes of the tunneling parameters A_k and B_k influenced by the drain-source voltage are also incorporated in the predicted model.The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages,silicon film thicknesses,gate dielectric layer thicknesses,and gate dielectric layer constants.Therefore,it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.
A 2-D semi-analytical model of double gate (DG) tunneling field-effect transistor (TFET) is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. the expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane’s model. In particular, the changes of the tunneling parameters A_k and B_k are influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Wherefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.