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采用行间转移型面阵CCD KAI-1020作为图像传感器,以现场可编程门阵列(FPGA)为核心控制器,设计并实现了一个完整的成像系统。FPGA产生驱动时序、控制CCD上电顺序、调节曝光时间,并实现数据缓存。CCD模拟视频信号经过预处理,通过同轴电缆传输到CCD专用视频处理器进行相关双采样和模数转换,以10位像素深度输出到FPGA,数字视频信号经过差分芯片驱动以低压差分信号(LVDS)格式输出到数据采集卡。集成化视频处理电路提高了系统的信噪比,改善了成像质量。实验表明,CCD成像系统工作稳定可靠,像素读出时钟为10MHz时,帧频为10帧/s。设计的CCD成像系统性能好、可靠性高、实现周期短,具有很强的可扩展性。
The line transfer CCD KAI-1020 is used as the image sensor, and a complete imaging system is designed and implemented based on field programmable gate array (FPGA). FPGA generates drive timing, control CCD power-on sequence, adjust the exposure time, and data cache. The CCD analog video signal is preprocessed, transmitted to the CCD dedicated video processor via a coaxial cable for correlated double sampling and analog-to-digital conversion, and output to the FPGA at 10-bit pixel depth. The digital video signal is driven by a differential chip with a low voltage differential signal (LVDS ) Format output to the data acquisition card. Integrated video processing circuit to improve the system’s signal to noise ratio, improved imaging quality. Experiments show that the CCD imaging system is stable and reliable. When the pixel readout clock is 10MHz, the frame rate is 10 frames / s. The designed CCD imaging system has good performance, high reliability, short implementation period and strong scalability.