With the growing needs for runtime flexibility,functional reliability and power efficiency,partially reconfigurable systems become increasingly promising platforms for computation-expensive applications.To overcome the architecture bottleneck of CPU,DSP,or GPU processors,this talk describes a unified reconfigurable architecture combining both bitstream configuration and data stream processing.It deploys high throughput point-to-point stream channels not only for inter-task communication,but also for partial bit stream configuration.User-defined hardware tasks can be dynamically reconfigured with reduced configuration time.Depending on different application requirements,system interconnection which supports dynamic configuration of multiple channels can be simultaneously established.To improve the system reliability,the proposed architecture can be used to refresh the corrupted configuration data,which can save a lot of hardware resources compared with the TMR approach.