Ge has been considered as one of the promising channel materials to repalace Si,for scaled devices in integrated circuits due to its high carrier mobilities.[1] Si-based Ge epilayer or Ge-oninsulator(GOI)materials are preferrred for Ge MOSFETs since the scarce of Ge source and their compatibility with Si technology.However,the large lattice mismatch between Si and Ge causes high dislocation denisty in Ge epilayers.[2] In viewpoint of Ge devices,high performance Ge pMOSFETs have been demonstrated.However,Ge device technology is far fiom mature and to realize well-behaved nMOSFET still faces more challenges.The charge neutrality level of Ge aligning near valance band edge makes it difficult to obtain high electron density in the channel and low Schottky barrier height between metal and n-Ge.The large diffusion coefficient and low activation efficiency of n-type dopants in Ge make it hard to achieve high n+ electrical activation and n+p shallow junction.[3]In this talk,an approach was proposed to grow high crystal quality Ge heterostructures on Si substrate with Ge coalecence islands buffer layer for reducing threading dislocations.Ultra thin GOI materials were prepared by local Ge condensation technique.The strain in the GOI can be modified significantly for high performance devices.In order to resolve the problem of n-type doping in Ge,excimer laser annealing was applied to phosphorus implanted Ge with a critical step of low temperature pre-annealing.Heavily doped n-type Ge of 2×10-20cm3 was obtained and a well-behaved Ge n+/p shallow junction with a record rectification ratio of~107 and low leakage current density of8.3×105A/cm2 was achieved.Those results will be great beneficial to the scaled Ge MOSFET technology.