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研究了基于电阻(R)电容(C)触发n型金属氧化物半导体(NMOS)器件的静电放电(ESD)电路参数与结构的设计,讨论了电阻电容触发结构对ESD性能的提升作用,研究了不同RC值对ESD性能的影响以及反相器结构带来的ESD性能差异,并讨论了在特定应用中沟道放电器件的优势。通过一系列ESD测试电路的测试和分析,发现电阻电容触发结构可以明显提高ESD电路的保护能力,其中RC值10 ns设计的栅耦合NMOS(GCNMOS)电路具有最高的单位面积ESD保护能力,达到0.62 mA/μm2。另外对于要求触发电压特别低的应用场合,RC值1μs设计的GCNMOS电路将是最好的选择,ESD能力可以达到0.47 mA/μm2,而触发电压只有3 V。
The design of parameters and structure of electrostatic discharge (ESD) circuit based on resistance (R) capacitor (C) to trigger n-type metal oxide semiconductor (NMOS) devices is studied. The effect of resistance and capacitance triggering structure on ESD performance is discussed. The effect of different RC values on ESD performance and the difference in ESD performance caused by the inverter structure are discussed and the advantages of channel discharge devices in specific applications are discussed. Through the testing and analysis of a series of ESD test circuits, it is found that the resistor-capacitor triggered structure can significantly improve the protection capability of the ESD circuit. The gate-coupled NMOS (GCNMOS) circuit with RC value of 10 ns has the highest ESD protection per unit area, reaching 0.62 mA / μm2. In addition, GCNMOS circuits with RC values of 1μs will be the best choice for applications requiring exceptionally low triggering voltage, with ESD capability of 0.47 mA / μm 2 and trigger voltage of only 3 V.