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以图形处理、数字信号处理等为代表的流应用,对微处理器提出了高并行度、高性能和高带宽的要求。针对流应用加速的流处理器体系架构得到了广泛研究。流体系结构大多集成大量的功能单元、开发多层次并行和存储来加速流应用,但同时增加了系统功耗和芯片面积。分析和比较了近年来主流的流处理器架构,提出了一种用于流应用加速的可重构协处理器。该协处理器针对流应用特点,实现了数据级和指令级并行,并集成了多个可以动态配置的运算单元,可动态配置其运算类型和数据类型,提升系统灵活性,降低芯片面积。针对典型算法,该处理器实现了更高的加速比,综合后延时为9.74ns,功耗为63.69mW。
Streaming applications, represented by graphics and digital signal processing, have raised the demand for high parallelism, high performance and high bandwidth for microprocessors. The stream processor architecture for streaming application acceleration has been extensively studied. Most of the fluidic architectures integrate a large number of functional units, developing multi-level parallelism and storage to accelerate streaming applications, while increasing system power consumption and chip area. Analyzed and compared the mainstream stream processor architecture in recent years, a reconfigurable coprocessor for stream application acceleration was proposed. The co-processor for the flow characteristics of the application, to achieve the data-level and instruction-level parallel, and integrates multiple dynamic configuration of the computing unit can dynamically configure its operation types and data types to enhance system flexibility and reduce chip area. For the typical algorithm, the processor achieves a higher speedup, with a combined delay of 9.74ns and a power dissipation of 63.69mW.