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用10块4000系列 CMOS 逻辑集成电路和少量无源元件就能使低频数字信号转换为高频字信号。按图1连接成的电路,产生频率转换为 fout=600×fin,其中系数600是由在节点A和B之间接的三块4018组成的 n 分频计数规定的。自激振荡器 1C_(1c)将频率近似为250KHz 的信号馈给电路中的计数器链,同时每经过一个输入频率 fin 的循环周期,4040二进制计数器便复零一次,使4040借助于从 B 节点的输出计数来测量输入周期。输入周期(12位二进制字)通过两块40174门锁存起来并馈给三块用4029构成的同步模 n 减计数器,这个计数器的各个输出产生一个 fout 脉冲,作为复零信号再反馈到4029门使其复零,从而为下一个周期的计数减作准备。
With 10 4000 series CMOS logic integrated circuits and a small number of passive components can make low-frequency digital signals into high-frequency word signal. The circuit connected as shown in Figure 1 generates a frequency transition fout = 600 × fin, where the coefficient 600 is specified by the n-division count of three 4018s connected indirectly between nodes A and B. FIG. The self-oscillating 1C_ (1c) feeds a signal of approximately 250 KHz in frequency to the counter chain in the circuit, and each cycle of the input frequency fin, the 4040 binary counter is reset to zero, The output count to measure the input period. The input period (12-bit binary word) is latched by two 40174 gates and fed to three synchronous n down counters, each consisting of 4029. The output of this counter produces a fout pulse, which is fed back as a complex zero signal to 4029 gates Reset it to zero, thereby preparing for the next cycle’s subtraction.