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在雷达信号处理过程当中,雷达信号的采集和存取是雷达系统重要的环节,由于ADC的采样速率,数据的宽度与DSP的时钟和宽度并不相同,为了保证两种之间的数据正确传输,基于FPGA的FIFO解决了这样的问题。文章介绍了DSP的EMIF(外部存储器接口)与异步FIFO(先进先出)存储器的基本结构和原理。着重阐述了EMIF如何读取FIFO存储器的数据,硬件的连接和软件的控制。通过实验测试,该设计方案实现雷达信号数据的正确传输。
In the process of radar signal processing, radar signal acquisition and access is an important part of the radar system. Due to the sampling rate of the ADC, the width of the data is not the same as the clock and width of the DSP. In order to ensure correct data transmission between the two FPGA-based FIFO solves this problem. The article introduces the DSP’s EMIF (external memory interface) and asynchronous FIFO (first-in, first-out) memory basic structure and principles. It highlights how EMIF reads FIFO memory data, hardware connections, and software control. Through experimental testing, the design program to achieve the correct transmission of radar signal data.