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依据JEDEC标准采用板级跌落实验研究晶圆级芯片尺寸封装Sn-3.0Ag-0.5Cu焊点的跌落失效模式。发现存在六种失效模式,即发生在印刷电路板(PCB)侧的短FR-4裂纹和完全FR-4裂纹,以及发生在芯片侧的再布线层(RDL)与Cu凸点化层开裂、RDL断裂、体钎料裂纹及体钎料与界面金属间化合物(IMC)混合裂纹。对于最外侧的焊点,由于PCB变形量较大且FR-4介质层强度较低,易于形成完全FR-4裂纹,其可吸收较大的跌落冲击能量,从而避免了其它失效模式的发生。对于内侧的焊点,先形成的短FR-4裂纹对跌落冲击能量的吸收有限,导致在芯片侧发生失效。
Based on the JEDEC standard, a drop-on-board experiment was conducted to investigate the drop failure mode of Sn-3.0Ag-0.5Cu solder bumps in wafer-level chip scale package. Six failure modes were found, namely, a short FR-4 crack and a complete FR-4 crack occurring on a printed circuit board (PCB) side, and a crack on the chip side rewiring layer (RDL) and a Cu bump layer, RDL fracture, bulk brazing alloy crack and interfacial intermetallic compound (IMC) mixed crack. For the outermost solder joints, a complete FR-4 crack is easily formed due to the larger deformation of the PCB and the lower strength of the FR-4 dielectric layer, which can absorb large drop impact energy and thus avoid other failure modes. For the inner solder joints, the first formed short FR-4 cracks have a limited absorption of drop impact energy, resulting in failure on the chip side.