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阐述了一种24×24bit+48bit带饱和处理的乘加单元的优化设计.在乘法器的设计中,采用改进的Booth算法,并将被加数作为乘法器的一个部分积参与到Wallace树阵列中来完成乘加运算,大大提高了MAC的性能,同时还设计出优化的饱和检测逻辑电路.利用0.18μm1.8V1P6M标准CMOS工艺通过全定制方式实现了面积为679.2μm×132.5μm的带饱和处理的MAC单元,仿真结果表明:它与软件设计系统综合出的传统MAC单元相比,性能上有很大的改善,在节约23.52%的面积情况下速度也有一定的提高.
A 24 × 24bit + 48bit optimal design of multiply-add unit with saturation processing is described in this paper.In the design of multiplier, an improved Booth algorithm is adopted and the addend is taken as a partial product of the multiplier to Wallace tree array To complete the multiply-add operation, greatly improving the performance of the MAC, but also to design an optimized saturation detection logic circuit using 0.18μm1.8V1P6M standard CMOS process through a fully customized way to achieve an area of 679.2μm × 132.5μm with saturation The simulation results show that compared with the traditional MAC unit integrated by the software design system, the performance of the MAC unit is greatly improved, and the speed is also improved with the area saving of 23.52%.