论文部分内容阅读
设计了一种新型时钟稳定电路—差分脉宽控制电路。用参考电路产生参考电压,避免因采用环形振荡器等方法产生大的时钟抖动。同时,在控制电路部分用交叉耦合正反馈来调节时钟占空比。该电路采用0.18μm工艺,电源电压为1.9 V,输入时钟占空比调节范围为25%~75%,时钟频率为2 GHz,时钟抖动小于200 fs。
A new type of clock stabilization circuit - differential pulse width control circuit is designed. The reference voltage is generated by the reference circuit to avoid large clock jitter due to the use of a ring oscillator or the like. At the same time, the cross-coupled positive feedback is used in the control circuit to adjust the clock duty cycle. The circuit uses a 0.18μm process, the supply voltage of 1.9 V, the input clock duty cycle adjustment range of 25% to 75%, the clock frequency is 2 GHz, the clock jitter is less than 200 fs.