日本电电公司武藏野电气通信研究所研制出高速低功耗正常截止型 GaAsMESFET 逻辑。其主要工艺特征是:1.用阳极氧化工艺精确控制外延层厚度;2.对亚微米栅的光刻要求欧姆接触层平整,并有陡的边缘,为此在合金处理前用磁控溅射 SiO_2膜覆盖片子表面,这可使表面不平度小于100(?)(不用 SiO_2膜时为1000(?)),用剥离工艺形成源和漏图形;3.用氩离子铣和化学腐蚀作 FET 的台面隔离,台面边缘是缓变的,可避免布线金属断裂;4.用 Japan's Musashino Electric Musashi Institute of Electrical Communication developed high-speed low-power normal cut-off GaAsMESFET logic. The main process features are: 1. Anodization process to precisely control the thickness of the epitaxial layer; 2. Sub-micron gate lithography requires ohmic contact layer formation, and has steep edges, so before the alloy treatment by magnetron sputtering SiO 2 film covering the surface of the film, which can make the surface roughness less than 100 (?) (1000 (?) Without SiO 2 film), the stripping process to form the source and drain patterns; 3. Argon ion milling and chemical etching FET Table isolation, the edge of the table is slowly changing, to avoid wiring metal rupture;