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数字抽取滤波器是Sigma-Delta(Σ-Δ)模数转换器(ADC)的重要组成部分,它负责Σ-Δ调制器输出信号的滤波和抽取。文中设计的数字抽取滤波器由级联积分梳状(CIC)滤波器、CIC补偿滤波器和半带滤波器组成。首先,介绍Σ-ΔADC原理;然后,讨论数字抽取滤波器的原理及实现;接着,分别从MATLAB和Verilog实现验证抽取滤波器的功能;最后,通过测试实际芯片验证数字抽取滤波器的功能和性能,满足设计要求。
Digital decimation filters are an important part of a Sigma-Delta analog-to-digital converter (ADC) that takes care of the filtering and decimation of the sigma-delta modulator output signal. The digital decimation filter designed in this paper consists of Cascaded Integral Comb (CIC) filter, CIC compensation filter and half-band filter. Firstly, the principle of Σ-Δ ADC is introduced. Then, the principle and implementation of digital decimation filter are discussed. Then, the function of decimation filter is validated from MATLAB and Verilog respectively. Finally, the function and performance of digital decimation filter are verified by testing the actual chip ,Meet the design requirements.