论文部分内容阅读
射极功能逻辑(EFL)是一类新的逻辑电路。为了便于大规模集成(LSI),在设计上它采用了非反相门结构,在相同的功耗水平,EFL的传递时延比反相门结构的更短;使用较低的电源电压,故其功耗可减少。其逻辑设计简单,因为无须转换便能直接实现最小化布尔代数方程,即它是采用“与”和“或”功能进行设计,而不是“与非”和“或非”功能设计,采用多发射极晶体管,并且合并几个多发射极晶体管作在同一隔离岛上,可使门结构有良好的面积效率。甚至沿用保守的双极结隔离工艺,也能实现有2～5PJ这样较好的功耗延迟乘积。
Emitter function logic (EFL) is a new class of logic. In order to facilitate large-scale integration (LSI), it is designed with a non-inverting gate structure, the same power consumption level, EFL transmission delay than the inverse gate structure is shorter; the use of lower power supply voltage, so Its power consumption can be reduced. Its logic design is simple because it minimizes the Boolean algebra equation without conversion, ie it is designed with AND and OR functions, not NAND and NOR functions, multiple emission Pole transistors, combined with several multi-emitter transistors on the same isolation island, provide a good area efficiency of the gate structure. Even with conservative bipolar junction isolation process, but also to achieve such a good 2 ~ 5PJ power delay product.