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一种面向多应用片上网络系统的拓扑尺寸开发流程被提出.该开发流程利用片上网络拓扑结构、任务映射算法以及应用任务图描述等要素产生多应用片上网络系统的系统映射方案,并在基于FPGA的片上网络验证平台上,对不同拓扑尺寸下的系统映射方案进行性能评估.实验表明,根据验证平台所提供的数据传输延迟和FPGA占用率,该开发流程有助于设计者在进行多应用片上网络系统设计时快速准确地找到每一个应用所对应的最适当的拓扑尺寸,从而提高系统的传输性能.
A topology size development process for multi-application system-on-chip is proposed. The development process utilizes the on-chip network topology, task mapping algorithm and application task graph description to generate the system mapping scheme of multi-application on-chip network system. On-chip network verification platform to evaluate the performance of system mapping schemes with different topological sizes.Experiments show that based on the data transmission delay and FPGA occupancy rate provided by the verification platform, the development process can help designers to implement multi-application on-chip Network system design quickly and accurately find each application corresponds to the most appropriate topology size, thereby enhancing the system’s transmission performance.