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本文对多元逻辑电路的主要基本单元线性“与或”门进行了进一步的分析和研究。提出了一种JFET偏置结构,推导了平均传播延迟的分析表达式,建立了晶体管增益与电路参数的关系方程,分析了电路在级联时低电平升高的物理原因。本研究工作采用泡发射极工艺。典型的平均级延迟为0.3ns,功耗延迟积为2.1pJ。实验结果表明,多元逻辑电路是一种有前途的极高速双极型电路。
This paper further analyzes and studies the linear OR gates of the main basic elements of multivariate logic circuits. A JFET bias structure is proposed. The analytical expression of average propagation delay is deduced. The equation of transistor gain and circuit parameters is established, and the physical reason why the low level rises when the circuit cascades is analyzed. The research work using bubble emitter process. The typical average delay is 0.3ns and the power delay product is 2.1pJ. The experimental results show that the multivariate logic circuit is a promising very high speed bipolar circuit.