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详细讨论了在高速PCB设计中最常见的公共时钟同步(COMMONCLOCK)和源同步(SOURCESYNCHRONOUS)电路的时序分析方法,并结合宽带网交换机设计实例在CADENCE仿真软件平台上进行了信号完整性仿真及时序仿真,得出用于指导PCB布局、布线约束规则的过程及思路。实践证实,在高速设计中进行正确的时序分析及仿真对保证高速PCB设计的质量和速度十分必要。
This paper discusses in detail the timing analysis methods of COMMONCLOCK and SOURCESYNCHRONOUS circuit, which are the most common in high-speed PCB design. The signal integrity simulation and timing are carried out on the CADENCE simulation software platform in combination with the design examples of broadband network switches Simulation, derived for guidance PCB layout, wiring constraints rules process and ideas. Practice has proved that the correct timing analysis and simulation in high-speed design to ensure high-speed PCB design quality and speed is necessary.