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微波单片集成电路(MMIC)数字衰减器的尺寸是芯片成本最主要的决定因素。基于GaAs E/D PHEMT工艺,研制了一款超小型DC~18 GHz 6 bit数字衰减器,芯片上集成了4 bit反相器。重点介绍了数字衰减器拓扑结构的改进及反相器的逻辑单元等电路设计的关键点。通过在衰减器拓扑中共用接地通孔、合并两个小衰减位、缩小微带线宽度和线间距、缩小薄膜电阻尺寸、减少控制电压压点个数,实现了芯片的超小型化,从而降低了MMIC数字衰减器的成本。测试结果表明,在DC~18 GHz频段内,数字衰减器的插入损耗小于6 d B,全态输入输出驻波比(VSWR)小于1.6,全态均方根误差小于0.7 d B,工作电流小于5 m A。数字衰减器芯片面积为1.45 mm×0.85 mm。
The size of the microwave monolithic integrated circuit (MMIC) digital attenuator is the most important determinant of chip cost. Based on the GaAs E / D PHEMT process, an ultra-compact DC ~ 18 GHz 6-bit digital attenuator has been developed with an integrated 4-bit inverter on the chip. The key points of improving the topological structure of the digital attenuator and the circuit design of the logic cell of the inverter are introduced emphatically. By combining common ground vias in the attenuator topology, combining two small attenuation bits, narrowing the microstrip line width and line spacing, reducing the size of the thin film resistors and reducing the number of control voltage pads, the chip is miniaturized and thus reduced MMIC digital attenuator costs. The test results show that the insertion loss of the digital attenuator is less than 6 d B in DC ~ 18 GHz, the VSWR is less than 1.6, the total RMSE is less than 0.7 d B, the operating current is less than 5 m A. The digital attenuator chip area is 1.45 mm × 0.85 mm.