设计并实现了一种12位40 MSPS流水线A/D转换器,并在0.18μm HJTC CMOS工艺下流片。芯片工作电压为3.3 V,核心部分功耗为99.1 mW。为优化ADC功耗,采用多位/级的系统结构和套筒式运放结构,并采用逐级按比例缩小的设计方法进一步节省功耗。测试结果表明,A/D转换器的DNL小于0.46 LSB,INL小于0.86 LSB;采样率为40 MSPS时,输入19.1MHz信号,SFDR超过80 dB,SNDR超过65 dB。 A 12-bit, 40 MSPS pipelined A / D converter was designed and implemented and run on a 0.18μm HJTC CMOS process. Operating voltage of 3.3 V chip, the core part of the power consumption of 99.1 mW. To optimize ADC power consumption, a multi-bit / level system architecture and a sleeve op amp architecture are used, with further step-by-step scaling to save power. The test results show that the A / D converter has a DNL of less than 0.46 LSB and an INL of less than 0.86 LSB. When the sample rate is 40 MSPS, a 19.1 MHz signal is input with SFDR exceeding 80 dB and SNDR exceeding 65 dB.