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随着集成电路工艺尺寸不断缩小,电路规模不断增大,要得到很高的小时延故障覆盖率所需的测试向量越来越多,致使小时延故障模拟成本越来越高.为了降低模拟成本,提出一个高效的小时延故障模拟器.模拟方法中引入新的波形表达方式,按电路结构的拓扑顺序进行分级模拟,最后可得到每个故障的检测区间,并且应用时延故障概率分布来计算故障覆盖率.实验结果表明,此方法能大幅降低模拟时间和内存消耗.
With the continuous shrinking of the size of the integrated circuit and the increasing of the circuit scale, more and more test vectors are needed to obtain a high coverage of the small delay fault, resulting in higher and higher simulation costs of the small delay fault.In order to reduce the simulation cost , An efficient small delay fault simulator is proposed.A new waveform representation is introduced into the simulation method and the simulation is performed according to the topological order of the circuit structure. Finally, the detection interval of each fault can be obtained, and the probability distribution of the fault delay can be used to calculate Fault coverage.The experimental results show that this method can significantly reduce the simulation time and memory consumption.