For real-time jamming signal generation in deceiving inverse synthetic aperture radar(ISAR),the target characteristics modulation is always processed in the expensive field programmable gate array(FPGA).Due to the large computational complexity of the traditional modulating operation,the size and structure of simulated false-target are limited.With regard to the principle of dechirping in range compression of linear frequency modulated(LFM) radar,a novel algorithm named “inverse dechirping” is proposed for target characteristics modulation.This algorithm only needs one complex multiplier in the FPGA to generate the jamming signal when the radar signal is intercepted,which can be obtained by multiplication of radar signal samplings and the equivalent dechirped target echo in the time domain.As the complex synthesis of dechirped target echo can be realized by cheap digital signal processor(DSP) within the interpulse time,the overall cost of the jamming equipment will be reduced and the false-target size will not be limited by the scale of FPGA.Numerical simulations are performed to verify the correctness and effectiveness of the proposed algorithm. For real-time jamming signal generation in deceiving inverse synthetic aperture radar (ISAR), the target characteristics modulation is always processed in the expensive field programmable gate array (FPGA) .Due to the large computational complexity of the traditional modulating operation, the size and structure of simulated false-target are limited. Whith regard to the principle of dechirping in range compression of linear frequency modulated (LFM) radar, a novel algorithm named “inverse dechirping” is proposed for target characteristics modulation. This algorithm only needs one complex multiplier in the FPGA to generate the jamming signal when the radar signal is intercepted, which can be obtained by multiplication of radar signal samplings and the equivalent dechirped target echo in the time domain. As the complex synthesis of dechirped target echo can be realized by cheap digital signal processor (DSP) within the interpulse time, the overall cost of the jamming equipment will be reduced and the false-target size will not be limited by the scale of FPGA. Numerical simulations are performed to verify the correctness and effectiveness of the proposed algorithm.