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研究了一种具有浮栅结构的SOI LDMOS(FGSOI LDMOS)器件模型,并分析了该结构的耐压机理,通过Silvaco TCAD软件对该结构进行仿真优化。通过仿真验证可知,该结构通过类场板的结终端技术可以调节器件的横向电场,从而得到比普通SOI LDMOS器件更高的耐压并且降低了器件的比导通电阻。仿真结果表明,该结构与普通SOI LDMOS器件结构在相同的尺寸条件下耐压提高了41%,比导通电阻降低了21.9%。
A SOI LDMOS (FGSOI LDMOS) device model with floating gate structure was studied. The breakdown voltage mechanism of the SOI LDMOS was analyzed. The structure was optimized by Silvaco TCAD software. The simulation results show that the structure can adjust the lateral electric field of the device through the junction termination technology of the field plate so as to obtain a higher withstand voltage than the conventional SOI LDMOS device and reduce the specific on-resistance of the device. Simulation results show that the structure and ordinary SOI LDMOS device structure in the same size under the conditions of pressure increased by 41%, 21.5% lower than the on-resistance.