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本文引入了一个概率空间来描述集成电路合格率优化问题，并将合格率表示为可行域的概率测度。所提出的变权重ＭｏｎｔｅＣａｒｌｏ法适合于合格率不太高的场合，而改进后的ＳＡ算法则适合于合格率比较高的场合。这些方法已应用于ＹＯＳＩＣ系统中，并取得了满意的效果。
This paper introduces a probabilistic space to describe the optimization of the pass rate of IC, and the pass rate is expressed as the probability measure of feasible region. The proposed Monte Carlo method with variable weight is suitable for the case where the pass rate is not too high, while the improved SA algorithm is suitable for the case with high pass rate. These methods have been applied to YOSIC system and have achieved satisfactory results.