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设计了一种高效的多码率LDPC(Low Density Parity Check)码译码器结构,提出了一种校验节点更新单元(CNU,Check Node Updating Units)与变量节点更新单元(VNU,Variable Node Updating Units)的设计方法.按照“化整为零”的思想,将CNU与VNU分成若干小的运算单元,在不同码率下对这些运算单元进行动态组合构成新的CNU与VNU,从而减少不同码率下硬件资源的冗余,提高了译码速率.最后,按照本文提出的译码器结构,使用Altera公司Stratix系列的FPGA EP1S80实现了中国数字电视地面广播传输标准中使用的0.4,0.6和0.8三种码率LDPC码的译码器.实现结果表明:该结构的多码率译码器仅比单码率译码器多耗用12%的硬件逻辑资源,存储器相当;而相对于传统的多码率译码器结构,本结构在不增加硬件资源的情况下,将0.4码率码字的译码速率提高了100%,将0.6码率码字的译码速率提高了50%.
An efficient Low Density Parity Check (LDPC) code decoder architecture is designed. A Check Node Updating Unit (CNU) and a Variable Node Updating Unit (VNU) are proposed. Units) .According to the idea of “rounding to zero ”, CNU and VNU are divided into several small arithmetic units, which are dynamically combined at different bit rates to form a new CNU and VNU, thus reducing At the same time, according to the structure of the decoder proposed in this paper, the FPGA EP1S80 of Altera Corporation Stratix series is used to realize the 0.4,0.6 standard used in China’s digital terrestrial television broadcasting standard And 0.8 three kinds of code rate LDPC code decoder.The implementation results show that: the structure of the multi-rate decoder consumes only 12% more hardware logic resources than the single-rate decoder, the memory is equivalent; and relative to The traditional multi-rate decoder structure, the structure without increasing the hardware resources, the 0.4 code rate code word decoding rate increased by 100%, 0.6 code rate code word decoding rate increased by 50% .