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针对一种新型的多压点复杂硅片电学测试(WET)结构,采用键合技术结合光束导致电阻变化(OBIRCH)缺陷隔离设备,定位芯片异常结构。之后利用扫描电子显微镜(SEM)对平面剥层后的样品进行表面观察,再利用聚焦离子束(FIB)切割仪和透射电子显微镜(TEM)对芯片做进一步的剖面结构物理分析,进而确定导致芯片性能异常的原因。通过手工键合把需要加相同测试条件的金属压点连接在印刷电路板(PCB)或引线框架的同一个电极上,以减少电性能测量时实际所需连接的金属压点的数目,成功确定了特征尺寸为0.11μm的逻辑电路失效产品的两个WET参数失效的根本原因。
Aiming at a new type of multi-voltage point complex silicon wafer electrical test (WET) structure, bonding technology combined with optical beam induced resistance change (OBIRCH) defect isolation device is used to locate the abnormal structure of the chip. After that, the surface of the flat peeled sample was observed with a scanning electron microscope (SEM), and further the cross-sectional structural physical analysis of the chip was performed by using a focused ion beam (FIB) cutter and a transmission electron microscope (TEM) The reason for abnormal performance. By manually bonding the need to add the same test conditions of the metal pressure points connected to the printed circuit board (PCB) or lead frame on the same electrode to reduce the electrical properties of the actual measurement required to connect the number of metal pressure points successfully identified The root cause of the failure of two WET parameters for logic circuit failure products with a feature size of 0.11 μm.