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本文讨论了一阶递归型数字滤波器的硬件设计,由建立数学模型到确定相应的硬件逻辑。给出了实验结果,并用软件在DJS—6计算机上得到验证。
This article discusses the first-order recursive digital filter hardware design, from the establishment of mathematical models to determine the appropriate hardware logic. The experimental results are given and verified by software on the DJS-6 computer.