随着极大规模集成电路的发展,芯片中的互连线密度不断增加,互连线的宽度和间距不断减小,因此由互连电阻(R)和电容(C)所产生的寄生效应越来越明显,进而使信号发生严重延迟。为解决这一问题,最有效的方法是使用低介电常数互联材料。目前业界普遍使用造孔技术,将空气引入到固体薄膜的微孔中。由于空气的介电常数为1,如此可以大幅度降 With the development of very large scale integrated circuits, the interconnect density in the chip is increasing and the width and spacing of interconnects are decreasing. Therefore, the parasitic effect caused by the interconnect resistance (R) and the capacitor (C) The more obvious, and then the signal serious delay. To solve this problem, the most effective method is to use low dielectric constant interconnect material. At present, the industry generally uses hole making technology to introduce air into the pores of the solid film. Since the dielectric constant of air is 1, this can be drastically reduced