【摘 要】
：
针对集成电路的规模和复杂度不断增加而相应的测试却越来越困难的问题,本文提出了一种基于三值神经网络的组合电路测试生成算法。该算法不需要传播,也不需要回退,而是利用三
【机 构】
：
哈尔滨理工大学测控技术与通信工程学院,
论文部分内容阅读
针对集成电路的规模和复杂度不断增加而相应的测试却越来越困难的问题,本文提出了一种基于三值神经网络的组合电路测试生成算法。该算法不需要传播,也不需要回退,而是利用三值神经网络把组合电路表示成双向的神经网络,并构造网络的能量函数,用遗传算法求解能量函数的最小值点来求得测试矢量,这样就把组合电路的测试生成问题转化为数学问题:在一些基准电路上的实验结果表明本算法具有较高的故障覆盖率和较短的测试时间:
In view of the problem that the scale and complexity of integrated circuits are increasing while the corresponding test is more and more difficult, this paper presents a combined circuit test generation algorithm based on three-valued neural network. The algorithm does not need to spread and does not need to back-off. Instead, the three-valued neural network is used to represent the combinational circuit as a two-way neural network and to construct the energy function of the network. The genetic algorithm solves the minimum point of the energy function to obtain the test Vector, so that the test circuit generation problems into mathematical problems: the experimental results on some of the benchmark circuit shows that the algorithm has a higher fault coverage and shorter test time:
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