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本文讨论由于实际基区层的扩散问题与在比较大的面积上可得到的光刻分辨率所产生的对功率晶体管性能的极限。图1表示一个典型的几何结构,其中L_e是发射极条的半宽度,两发射极之间的距离为2L_e,总的发射极周长为L_p。发射极面积为A_e=L_eL_p,集电极面积为A_c=2L_eL_p。发射极平面的基区层的薄层电阻为R_s,由I_n所表示的载流子的渡越时间为τ,它与截止频率f=1/2πτ相对应,而集电极电阻率由集电极体击穿电压V_B来描述。我们将考虑增益、功率输出和阻抗与上述参数有什么关系,以及如何估计用现有工艺所能得到的性能。
This article discusses the limits on power transistor performance due to the diffusion of the actual base layer and the lithographic resolution available over a relatively large area. Figure 1 shows a typical geometry where L_e is the half-width of the emitter strip, the distance between the two emitters is 2L_e and the total emitter circumference is L_p. The emitter area is A_e = L_eL_p and the collector area is A_c = 2L_eL_p. The sheet resistance of the base layer of the emitter plane is R_s, the transit time of the carrier represented by I_n is τ, which corresponds to the cut-off frequency f = 1 / 2πτ and the collector resistivity is determined by the collector body Breakdown voltage V_B to describe. We will consider the gain, power output and impedance and the above parameters have any relationship, and how to estimate the performance available with existing technology.