目前自激振荡线路驱动器由于极限环频率较低,在输入信号频率较高时,系统增益下降较大,由延时决定的自激振荡线路驱动器可提高极限环频率。本文分析了提高极限环频率后系统增益、线性度和功耗等的变化,并采用0.25μm CMOS工艺设计了一个VDSL线路驱动器进行验证。实验结果表明,提高极限环频率可减小高频输入信号时系统增益的下降,且在一定范围内可提高线性度,但过高的极限环频率会引入过大的电源噪声和地噪声,恶化线性度。 At present, the self-excited oscillation line driver has a lower system frequency limit because of the lower limit frequency of the limit line. When the input signal frequency is high, the system gain drops a lot. The self-excited oscillation line driver determined by the delay increases the limit cycle frequency. This paper analyzes the changes of the system gain, linearity and power consumption after the limit cycle frequency is increased. A VDSL line driver is designed by 0.25μm CMOS process. The experimental results show that increasing the limit cycle frequency can reduce the system gain when high frequency input signal decreases and improve the linearity within a certain range, but too high limit cycle frequency will lead to excessive power supply noise and ground noise, worsening Linearity.