对FIR滤波器中的乘法如何在FPGA得到高效实现进行了研究。结合FPGA查找表结构,兼顾资源和速度的要求,采用改进的分布式算法,设计了20阶常系数FIR滤波器。在此基础上,用OBC编码对其查找表进一步优化。最后,在ISE13.1下进行综合,并在Modelsim下进行仿真,用Matlab分析得到的数据频谱,以确定达到设计效果。结果表明,该设计既节省了FPGA的资源占用,又提高了运行速度。 How the multiplication in the FIR filter is implemented efficiently in the FPGA is studied. Combined with the structure of FPGA lookup table and taking into account the requirements of resources and speed, a 20-order constant-coefficient FIR filter is designed with an improved distributed algorithm. On this basis, using OBC coding to further optimize its look-up table. Finally, under the ISE13.1 synthesis, and under Modelsim simulation, Matlab analysis of the resulting data spectrum to determine the design to achieve results. The result shows that this design not only saves the resource occupation of FPGA, but also improves the running speed.