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本文提出了一个适合ＶＬＳＩ测试仪需要的位独立访问存储结构的设计方案。文中介绍了该方案的逻辑结构，以及配合该方案的可编程脉冲源，并对该方案的性能进行了分析讨论。
This article presents a design that is suitable for the bit-independent access memory structure required by the VLSI tester. In this paper, the logical structure of the scheme and the programmable pulse source with the scheme are introduced, and the performance of the scheme is analyzed and discussed.