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为了降低传统增量型Σ-ΔADC在同精度情况下的量化时钟周期数,提高转换速率,提出了1种采用粗细量化的2步式增量放大型ADC.该ADC采用SAR ADC先进行6位粗量化,再采用增量型Σ-ΔADC进行8位高精度位的细量化,通过数字码拼接完成最终量化结果.同时引入了1种增益自举C类反相器技术,有效地降低了供电电压和整体功耗.该ADC使用0.18μm标准CMOS工艺进行了电路实现,在1.2 V供电电压,1 MHz采样频率、10 k S/s的转换速率的情况下,达到了81.26 d B的信噪失真比(SNDR)和13.21位的有效位数(ENOB),最大积分非线性为0.8 LSB.并且该ADC的整体功耗为197μW,可用于低电压低功耗的仪器测量和传感器等领域.
In order to reduce the number of quantized clock cycles and improve the conversion rate of the conventional incremental sigma-delta ADC at the same precision, a 2-step incremental amplification ADC with coarse and fine quantization is proposed. The ADC uses a 6-bit SAR ADC Coarse quantization, and then using incremental Σ-ΔADC fine-bit 8-bit high-precision, digital code splicing to complete the final quantification results.At the same time introduced a gain-C class inverter technology, effectively reducing the power supply Voltage and overall power consumption.The ADC is implemented in a 0.18μm standard CMOS process and achieves a signal-to-noise of 81.26 dB at a 1.2 V supply voltage, 1 MHz sampling rate, 10 ks / s slew rate Distortion ratio (SNDR), and 13.21 significant digits (ENOB), the maximum integrated nonlinearity is 0.8 LSB, and the overall power consumption of this ADC is 197μW, which can be used in the field of low voltage and low power instrument measurement and sensors.