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本文介绍一种由八个高压MOS器件组成的低高压MOS接口电路.它采用与目前国际上先进的NMOS大规模集成电路工艺技术完全兼容的N阱硅栅等平面CMOS工艺,而不需要附加任何工艺步骤.本文描述了高压MOS器件的物理模型,介绍了器件结构和工艺设计,并给出了高压MOS器件的漏击穿电压时沟道长度、漂移区长度、离子注入剂量和延伸源场极的关系的实验结果.这种高压MOS器件的漏击穿电压最大可达400V(在零栅偏压时),最大饱和漏电流可达35mA(在栅压为10V时),而导通电阻低到600(?)(在栅压为10V时).
This article introduces a low-voltage MOS interface circuit composed of eight high-voltage MOS devices that uses a planar CMOS process such as an N-well silicon gate that is fully compatible with the world’s most advanced NMOS large-scale integrated circuit technology without the need for any additional Process steps.This paper describes the physical model of high-voltage MOS devices, introduces the device structure and process design, and gives the high-voltage MOS device leakage breakdown voltage channel length, drift region length, ion implantation dose and extended source field The leakage breakdown voltage of this high-voltage MOS device can reach up to 400V (at zero gate bias) and the maximum saturation leakage current can reach 35mA (at gate voltage of 10V), while the on-resistance is low To 600 (?) At a gate voltage of 10V.