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大型系统正在自己的模拟前端使用更多更快的通道,设计者必须为其选择CMOS、LVDS亦或CML输出。必须了解这些输出的主要特性、性能折衷,以及布局要求。当设计者有多种ADC选择时,他们必须考虑采用哪种类型的数字数据输出:CMOS(互补金属氧化物半导体)、LVDS(低压差分信令),还是CML(电流模式逻辑)。ADC中所采用的每种数字输出类型都各有优缺点,设计者应结合自己的应用来考虑。这些因素取决于ADC的采样速率与分辨率、输出数据速率,以及系统设计的功率要求,等等。
Large systems are using more and faster channels on their analog front ends, and designers have to opt for CMOS, LVDS, or CML outputs. You must understand the key features of these outputs, performance trade-offs, and layout requirements. When designers have multiple ADC options, they must consider which type of digital data output to adopt: CMOS, LVDS, or CML. Each type of digital output used in the ADC has advantages and disadvantages, designers should consider their own applications. These factors depend on the sampling rate and resolution of the ADC, the output data rate, and the power requirements of the system design, and so on.