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介绍了一种超高速 51 2 /2 56分频器电路的设计 ,其基本结构采用静态主从 D触发器。电路采用先进的单层多晶硅发射极双极工艺制造 ,使用 3μm设计规则 ,电路的最高工作频率达到 2GHz。
This paper introduces the design of an ultra-fast 51 2/2 56 frequency divider circuit. Its basic structure adopts static master-slave D flip-flop. Circuit using advanced single-layer polysilicon emitter bipolar process, the use of 3μm design rules, the maximum operating frequency circuit to 2GHz.