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In the space environment, Viterbi decoder implemented on SRAM-based FPGA is sensitive to Single event upsets(SEUs), which may lead to functional failure of the decoder. Conventional SEU mitigation techniques like modular redundancy could not exploit the characters of Viterbi decoders,therefore could not provide optimized SEU tolerance when the device resource utilization cost is a constraint. Leveraging the properties of the decoding algorithm, three effective mitigation techniques are adopted, including structure optimization, Error detection and correction(EDAC) for Block RAM(BRAM) protection, and Partial triple-modular redundancy(PTMR), which are applied to the modules of the decoder in accordance with their characteristics. Analysis of effectiveness shows that compared with unmitigated design, the SEU induced failure rate in the proposed SEU tolerant decoder can be reduced to 1/4 at the cost of 61.1% extra resource utilization.
In the space environment, Viterbi decoder implemented on SRAM-based FPGAs is sensitive to Single event upsets (SEUs), which may lead to functional failure of the decoder. Conventional SEU mitigation techniques like modular redundancy could not exploit the characters of Viterbi decoders, therefore Leveraging the properties of the decoding algorithm, three effective mitigation techniques are adopted, including structure optimization, Error detection and correction (EDAC) for block RAM (BRAM) protection, and Partial triple-modular redundancy (PTMR), which are applied to the modules of the decoder in accordance with their characteristics. Analysis of effectiveness that that compared with unmitigated design, the SEU induced failure rate in the proposed SEU tolerant decoder can be reduced to 1/4 at the cost of 61.1% extra resource utilization.