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提出了一种在45nm体硅工艺下使用双-栅氧化层厚度来降低整体泄漏功耗的方法.所提方法具有不增加面积和延时、改善静态噪声边界、对SRAM设计流程的改动很小等优点.提出了三种新型的SRAM单元结构,并且使用这些单元设计了一个32kb的SRAM,仿真结果表明,整体泄漏功耗可以降低50%以上.
A method of reducing the overall leakage power consumption by using double-gate oxide thickness in a 45nm bulk silicon process is proposed. The proposed method has the advantages of not increasing the area and delay, improving the static noise boundary, and minimizing the SRAM design flow Etc. Three new SRAM cell structures are proposed, and a 32kb SRAM is designed by using these cells. The simulation results show that the overall leakage power consumption can be reduced by more than 50%.