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A wideband fractional-N frequency synthesizer is implemented in a 65 nm CMOS process.It employs a wideband LC voltage-controlled oscillator(VCO) with optimized VCO gain(KVCO/and a sub-band step to improve automatic frequency calibration(AFC) efficiency at negligible expense of phase noise performance.An agile AFC is realized by direct mapping based on the division ratio,and optional redundant counting and comparing calibration is introduced accommodating PVT variations,which samples the reference clock using the prescaled VCO output as a discriminating clock.A charge pump with switched charging current is adopted to compensate for the loop bandwidth variation.Measurement results show this directly-mapped AFC locates the target sub-band in 100 ns and only needs 1.2 s for redundant calibration.The frequency synthesizer spans a frequency range from 0.62 to 1.52 GHz,with phase noise of-86 dBc/Hz at 10 kHz offset and-122 dBc/Hz at 1 MHz offset while consuming 9.76 mA from a 1.2 V supply.
A wideband fractional-N frequency synthesizer is implemented in a 65 nm CMOS process. It employs a wideband LC voltage-controlled oscillator (VCO) with optimized VCO gain (KVCO / and a sub-band step to improve automatic frequency calibration (AFC) efficiency at negligible expense of phase noise performance. An agile AFC is realized by direct mapping based on the division ratio, and optional redundant counting and comparing calibration is accommodating pars PVT variations, which samples the reference clock using the prescaled VCO output as a discriminating clock. A charge pump with switched charging current is taken to compensate for the loop bandwidth variation. Measurement result show this directly-mapped AFC locates the target sub-band in 100 ns and only needs 1.2 s for redundant calibration. The frequency synthesizer spans a frequency range from 0.62 to 1.52 GHz with phase noise of -86 dBc / Hz at 10 kHz offset and-122 dBc / Hz at 1 MHz offset while consuming 9.76 mA from a 1.2 V supply.