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HgCdTe e-APD工作于线性模式,通过内雪崩倍增效应将一个微弱的信号放大多个数量级。介绍了一个具有列共用ADC制冷型(77K)数字化混成式HgCdTe e-APD FPA读出电路,可以应用于门控3D-LARDAR成像,有主被动双模式成像功能。Sigma-delta转换器比较适合于中规模128×128焦平面列共用ADC。调制器采用2-1 MASH单比特结构,开关电容电路实现,数字抽取滤波器采用CIC级联梳状滤波器。采用GLOBALFOUNDRIES 0.35μm CMOS工艺,中心距100μm。设计了量化噪声抵消逻辑消除第一级调制器量化噪声,采用数字电路实现。CIC抽取滤波器的每一级寄存器长度以方差为指标截尾,以降低硬件消耗。并且数字抽取滤波器工作电压降低到1.5V,可以进一步降低功耗。仿真显示sigma-delta转换器精度大于13bit,功耗小于2.4mW,转换速率7.7k Samples/s。
HgCdTe e-APD operates in linear mode, amplifying a weak signal by orders of magnitude by the avalanche multiplication effect. This paper introduces a digitally mixed HgCdTe e-APD FPA readout circuit with column-shared ADC refrigeration (77K), which can be used in gated 3D-LARDAR imaging with active-passive dual-mode imaging. Sigma-delta converter is more suitable for medium-sized 128 × 128 focal plane array shared ADC. Modulator 2-1 MASH single-bit structure, the realization of switched capacitor circuit, the digital decimation filter CIC cascaded comb filter. Using GLOBALFOUNDRIES 0.35μm CMOS process, the center distance of 100μm. The quantization noise cancellation logic is designed to eliminate the quantization noise of the first stage modulator, which is realized by the digital circuit. The length of each register of the CIC decimation filter is truncated by the variance to reduce hardware consumption. And digital decimation filter operating voltage down to 1.5V, can further reduce power consumption. Simulation shows that sigma-delta converter accuracy is greater than 13bit, power consumption is less than 2.4mW, the conversion rate of 7.7k Samples / s.