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提出了一种用于H.264/AVC编解码器的通用并行变换结构,并利用Verilog语言进行了电路设计。该并行结构主要包含4个移位器和16个累加器,可以完成H.264/AVC中的全部4×4变换,包括4×4哈达马变换和4×4离散余弦变换和反变换,能够达到每个时钟周期处理一个像素点的速度。使用SMIC0.18μm工艺对该并行结构进行了综合,电路面积为3757门,工作在100MHz时钟频率下的关键路径为10.3ns.
A universal parallel conversion structure for H.264 / AVC codec is proposed and the circuit design is done by using Verilog language. This parallel architecture, consisting mainly of 4 shifters and 16 accumulators, performs all 4 × 4 transforms in H.264 / AVC, including 4 × 4 Hadamard transform and 4 × 4 discrete cosine transforms and inverse transforms, enabling Reach one pixel per clock cycle. The parallel structure is synthesized using a SMIC 0.18μm process, with 3757 gates and a critical path of 10.3ns at 100MHz clock frequency.