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在数字电路的设计中,经常碰到对时钟脉冲进行选通的问题。人们常用图1所示的受控门电路来解决。在图1的电路中,当控制端为高电平时,通过G_1反相;使G_2门处于关门状态,时钟脉冲不能通过G_2输出:当控制端为低电平时,G_2门处于开门状态,时钟脉冲被允许通过G_2输出。从面达到选通的目的。这种电路一般用在要求不太高的场合。因为在控制电平跳变时,在G_2的输出端可能会产生窄脉冲。从图2中的CP—1输出脉冲可以看出,第N个和第M个时钟脉冲的输出即为窄脉冲,而这个窄脉冲的宽度又是随
In the design of digital circuits, often encounter the problem of gating the clock pulse. People often use controlled gate shown in Figure 1 to solve. In the circuit of Fig. 1, when the control terminal is high level, it is inverted by G_1; the G_2 door is closed and the clock can not be output by G_2. When the control terminal is low level, the G_2 door is opened and the clock pulse Allowed to export via G_2. From the surface to achieve the purpose of gating. This circuit is generally used in less demanding situations. Because of the control level jump, the G_2 output may produce a narrow pulse. It can be seen from the CP-1 output pulse in FIG. 2 that the output of the Nth and Mth clock pulses is a narrow pulse, and the width of this narrow pulse is again