基于TSMC 0.18μm CMOS工艺,设计了一种低功耗约束下的CMOS低噪声放大器。与传统的共源共栅结构相比,该电路在共源晶体管的栅源间并联一个电容,以优化噪声;并引入一个电感,与级间寄生电容谐振,以提高增益;通过减小晶体管的尺寸,实现了低功耗。模拟结果表明,在2.45 GHz工作频率下,增益大于14 dB,噪声系数小于1 dB,直流功耗小于2 mW。 Based on the TSMC 0.18μm CMOS process, a low-power CMOS low-noise amplifier is designed. Compared with the traditional cascode structure, the circuit parallels a capacitor between the gate and the source of the source transistor to optimize the noise. An inductor is introduced to resonate with the interstage parasitic capacitance to increase the gain. Size, to achieve low power consumption. Simulation results show that at 2.45 GHz, the gain is greater than 14 dB, the noise figure is less than 1 dB, and the dc power dissipation is less than 2 mW.