A new loading-balanced architecture for high speed and low power consumption pipeline analog-todigital converter(ADC) is presented in this paper. The proposed ADC uses SHA-less, op-amp and capacitor-sharing technique, capacitor-scaling scheme to reduce the die area and power consumption. A new capacitor-sharing scheme was proposed to cancel the extra reset phase of the feedback capacitors. The non-standard inter-stage gain increases the feedback factor of the first stage and makes it equal to the second stage, by which, the load capacitor of op-amp shared by the first and second stages is balanced. As for the fourth stage, the capacitor and op-amp no longer scale down. From the system’s point of view, all load capacitors of the shared OTAs are balanced by employing a loadingbalanced architecture. The die area and power consumption are optimized maximally. The ADC is implemented in a 0.18 μm 1P6M CMOS technology, and occupies a die area of 1.2×1.2 mm~2. The measurement results show a 55.58 dB signal-to-noise-and-distortion ratio(SNDR) and 62.97 dB spurious-free dynamic range(SFDR) with a 25 MHz input operating at a 200 MS/s sampling rate. The proposed ADC consumes 115 m W at 200 MS/s from a 1.8 V supply. A new loading-balanced architecture for high speed and low power consumption pipeline analog-todigital converter (ADC) is presented in this paper. The proposed ADC uses SHA-less, op-amp and capacitor-sharing techniques, the die area and power consumption. A new capacitor-sharing scheme was proposed to cancel the extra reset phase of the feedback capacitors. The non-standard inter-stage gain increases the feedback factor of the first stage and makes it equal to the second stage , by which, the load capacitor of op-amp shared by the first and second stages is balanced. As for the fourth stage, the capacitor and op-amp no longer scale down. From the system’s point of view, all load capacitors of the The OTAs are balanced by employing a loading balanced architecture. The die area and power consumption are optimized maximally. The ADC is implemented in a 0.18 μm 1P6M CMOS technology, and occupies a die area of ​​1.2 × 1.2 mm ~ 2. The measurement results show a55.58 dB signal-to-noise-and-distortion ratio (SNDR) and 62.97 dB spurious-free dynamic range (SFDR) with 25 MHz input operating at 200 MS / s sampling rate. MS / s from a 1.8 V supply.