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采用电化学电容-电压(ECV)法对等离子体掺杂制备的Si超浅p+n结进行了电学表征.通过对超浅p+n结样品ECV测试和二次离子质谱(SIMS)测试及比较,发现用ECV测试获得的p+层杂质浓度分布及结深与SIMS测试结果具有良好的一致性,但ECV测试下层轻掺杂n型衬底杂质浓度受上层高浓度掺杂影响很大.ECV测试具有良好的可控性与重复性.对不同退火方法等离子体掺杂形成的超浅结样品的ECV系列测试结果表明,ECV能可靠地表征结深达10nm,杂质浓度达1021cm-3量级的Si超浅结样品,其深度分辨率可达纳米量级,它有望在亚65nm节点CMOS器件的超浅结表征中获得应用.
The ultrathin p + n junction fabricated by plasma doping was characterized by electrochemical capacitance-voltage (ECV) method.The ECV and SIMS measurements of ultra-shallow p + n junction The results show that the impurity concentration distribution of p + layer and the junction depth obtained by ECV test are in good agreement with the results of SIMS test, but the impurity concentration of the lightly doped n-type substrate under ECV test is greatly affected by the high concentration doping of the upper layer. The test shows good controllability and repeatability.The results of ECV tests on ultra-shallow junctions formed by plasma doping of different annealing methods show that ECV can reliably characterize the junction depth of 10nm and the impurity concentration of 1021cm-3 Si ultra-shallow junctions with depth resolution up to nanometers and is expected to find applications in ultra-shallow junctions of sub-65nm node CMOS devices.